1. Technical Field
The present invention relates to mechanisms for bootstrapping computer systems, and in particular, to methods for bootstrapping multi-processor computer systems using hardware assistance.
2. Background Art
Bootstrapping is the process by which a computer is brought to its operating state from a powered-off state or following a reset event. The bootstrapping process typically begins with the processor(s) of the computer system and proceeds outward to system level resources. For many computer systems, bootstrapping begins with each processor in the system executing a built-in-self-test (BIST) that is stored on the processor chip in the form of micro-code. A processor executes this micro-code to test its internal components and to initialize certain processor registers. For example, the processor may read certain pins when a reset condition is detected, to determine its assigned identification number (xe2x80x9cprocessor IDxe2x80x9d). The micro-code store also provides a scratch pad that allows the processor to perform limited data manipulations.
Following the initial self-test portion of the bootstrap process, non-processor components of the computer system, such as memory, system logic, and peripheral devices, are tested and initialized. System-level initialization procedures include checking the integrity of memory, identifying and initializing non-processor components in the computer system, and loading the operating system into memory. For uni-processor systems, the single processor handles system-level initialization.
For multi-processor (MP) systems, a monarch or bootstrap processor (BSP) is selected from among the multiple processors to handle system-level initialization. In MP systems, initialization includes coordinating the other, non-BSP processors in addition to the procedures described above. For example, the BSP may signal the other processors to test their memory interfaces when the system memory is brought on line. One BSP-selection algorithm employs a message passing protocol to identify the processor having the highest numbered processor ID and to designate this processor as the BSP. This algorithm is described in U.S. Pat. No. 5,904,733, Bootstrap Processor Selection Architecture In Symmetric Multiprocessor Systems. 
BSP-selection algorithms may be stored as micro-code in each processor of the MP system, but this approach consumes additional processor die area and is less versatile. To reduce the impact on processor die area, some MP systems store the BSP selection algorithm as a firmware routine in a shared, non-volatile memory device. The use of off-chip storage also allows original equipment manufacturers (OEMs) to add their own BSP selection routines to a processor. The firmware implementation of the BSP selection algorithm is usually stored in a xe2x80x9chardware-protectedxe2x80x9d region of non-volatile memory. Hardware-protected firmware can not be altered without special equipment. It is used to preserve the core portions of the bootstrapping algorithm against events that could otherwise disable the computer system entirely.
Unlike micro-code, non-volatile memories do not provide a scratch pad for data manipulation. Firmware-based algorithms can still perform data manipulations, but the lack of a scratch pad makes these algorithms more complex to implement and debug. For example, the firmware implementation of the message-passing BSP-selection algorithm employs more instructions than the micro-code implementation, and a relatively large hardware-protected region of firmware is necessary to accommodate it. Since hardware-protected firmware can not be updated in the field, increasing the size of this region reduces the amount of updateable non-volatile memory available to the computer system. In addition, the relative complexity of firmware-implemented, BSP-selection routines makes them difficult to debug and port to different hardware platforms.
The present invention addresses these and other issues associated with BSP selection.
The present invention supports bootstrap processor selection in a multi-processor computer system, using a relatively compact firmware routine in combination with system logic.
A computer system in accordance with the present invention includes system logic having a sticky, e.g. write-once, register, multiple processors, and a firmware routine through which the processors may read and write the sticky register. When a reset event is detected, the processors vie for access to the sticky register, and the first processor that successfully writes its associated processor ID to the sticky register becomes the bootstrap processor.
For one embodiment of the invention, the sticky register is memory-mapped and the firmware routine includes a store instruction and a load instruction that target the memory-mapped address of the sticky register. The processor writes (stores) its processor ID to the sticky register, reads (loads) a value from the sticky register, and compares the read value to its processor ID. If the processor is the first to successfully write the sticky register, the read value matches the processor""s ID, and the processor proceeds with the bootstrap routine. Writes executed by subsequent processors to update the register are not recorded in the sticky register.